| 86h - EV6 detected ICache Tag or Data Parity Error |
| Indicator: |
EV6 -Pass 2.2 I_STAT<31:28> = 0010b for Tag ; 0100b for Data
EV6 Pass 3.0 I_STAT<29> = 1 for Tag or Data.
|
| Description: | The DECChip 21264 detected an ICache Tag or Data Parity read error. This EV6 Pass 2.2 error is uncorrectable and no PALcode action is performed other than to deliver the uncorrectable frame. On the EV6 Pass 3.0 error hardware posts this as correctable read data error. |
| Analysis: | C_ADDR Contains the physical address of the octaword associated with the error. |
| Recovery: | The EV6 Pass 2.2 hardware traps. The error is processed by the SRM Console PAL, UNIX and OpenVMS 660, and WNT Hal machine check handlers.
The EV6 Pass 3.0 hardware traps and replays the instructions that were fetched during the error, then flushes the entire ICache to insure the re-fetched instructions do not come directly from the failing cache context. The SRM console PALcode, UNIX and OpenVMS 630 and WNT HAL machine check handlers process this error. Typically this error condition will be threshold processed by the UNIX, OpenVMS, and WNT filters and logged by the appropriate error handler. |
| Faulting FRU: | |
| 204h - System ( 212xx PChip ) detected Single bit Correctable ECC Error |
| Indicator: | P0_CTL<18>= 1 and DIR0<62> = 1 and P0_ERROR<11>= 1 and P0_ERROR<51> = 0 from PCHIP0 or
P1_CTL<18>= 1 and DIR0<61> = 1 and P1_ERROR<11>= 1 and P1_ERROR<51> = 0 from PCHIP1 |
| Description: | A system single bit correctable DMA or S/G read error from PCI memory space has been detected by PChip 0 or 1. The 620-machine check handler processes this error. |
| Analysis: |
If PChip 0 error
P0_ERROR<63:56>, SYN, will contain the ECC Syndrome of the error
P0_ERROR<55:52>, CMD, will contain the type of DMA operation. Refer to Table 5-27 for the definitions
P0_ERROR<50:16>, ADDR, will contain the system address bits <34:3> of the erroneous quadword.
If PChip 1 error then
P1_ERROR<63:56>, SYN, will contain the ECC Syndrome of the error
P1_ERROR<55:52>, CMD, will contain the type of DMA operation. Refer to Table 5-28 for the definitions
P1_ERROR<50:16>, ADDR, will contain the system address bits <34:3> of the erroneous quadword.
|
| Recovery: | The PChip corrects the ECC data error within the longword (for single PCI access) or quadword (for dual-access cycle). Typically this error condition will be processed by the Operating System Memory CRD filter and the system operation typically requires no recovery unless CRD filtering thresholds have been exceeded. In this case the operating system should map out the related memory page and log the appropriate error event. |
| Faulting FRU: | Error detected in device or option and corrected during DMA reads. |
| 202h - System detected PCI Address Parity Error (SERR#) |
| Indicator: | DIR0<62> = 1 and P0_ERROR<1> = 1 and P0_ERROR<51> = 0 from PCHIP0 or
DIR0<61> = 1 and P1_ERROR<1> = 1and P1_ERROR<51> = 0 from PCHIP1 |
| Description: | PChip 0 or 1 has detected a PCI address parity error when acting as a master. This is processed through the 660-error handler. |
| Analysis: |
If PChip 0 error
P0_ERROR<55:52>, CMD, will contain the PCI Command of the transaction that caused the error.
P0_ERROR<47:18>, ADDR, will contain address bits <31:2> of the starting PCI Address of the transaction that caused the error.
P0_ERROR<17:16> will be 00b if not a DAC operation; 01b if via DAC SG to Window 3; and 1xb via monster window.
If PChip 1 error then
P1_ERROR<55:52>, CMD, will contain the PCI Command of the transaction that caused the error.
P1_ERROR<47:18>, ADDR, will contain address bits <31:2> of the starting PCI Address of the transaction that caused the error.
P1_ERROR<17:16> will be 00b if not a DAC operation; 01b if via DAC SG to Window 3; and 1xb via monster window.
|
| Recovery: | There is no recovery for this defective PCI target transaction. |
| Faulting FRU: | Option |
| 202h - System detected PCI Write Data Parity Error (PERR#) |
| Indicator: | DIR0<62> = 1 and P0_ERROR<2> = 1 and P0_ERROR<51> = 0 from PCHIP0 or
DIR0<61> = 1 and P1_ERROR<2> = 1and P1_ERROR<51> = 0 from PCHIP1 |
| Description: | PChip 0 or 1 detected a PCI write data parity error when acting as a master. This is processed through the 660-error handler. |
| Analysis: |
If PChip 0 error
P0_ERROR<55:52>, CMD, will contain the PCI Command of the transaction that caused the error.
P0_ERROR<47:18>, ADDR, will contain address bits <31:2> of the starting PCI Address of the transaction that caused the error.
P0_ERROR<17:16> will be 00b if not a DAC operation; 01b if via DAC SG to Window 3; and 1xb via monster window.
If PChip 1 error then
P1_ERROR<55:52>, CMD, will contain the PCI Command of the transaction that caused the error.
P1_ERROR<47:18>, ADDR, will contain address bits <31:2> of the starting PCI Address of the transaction that caused the error.
P1_ERROR<17:16> will be 00b if not a DAC operation; 01b if via DAC SG to Window 3; and 1xb via monster window.
|
| Recovery: | There is no recovery for this defective PCI target transaction. |
| Faulting FRU: | Option |
| 202h - System detected PCI Delayed Completion Retry Time Out Error (DCRTO) |
| Indicator: | DIR0<62> = 1 and P0_ERROR<3> = 1 and P0_ERROR<51> = 0 from PCHIP0 or
DIR0<61> = 1 and P1_ERROR<3> = 1and P1_ERROR<51> = 0 from PCHIP1 |
| Description: | A PCI delayed completion retry time out error has been detected by a target PChip 0 or 1. This is processed through the 660-error handler. |
| Analysis: |
If PChip 0 error
P0_ERROR<55:52>, CMD, will contain the PCI Command of the transaction that caused the error.
P0_ERROR<47:18>, ADDR, will contain address bits <31:2> of the starting PCI Address of the transaction that caused the error.
P0_ERROR<17:16> will be 00b if not a DAC operation; 01b if via DAC SG to Window 3; and 1xb via monster window.
If PChip 1 error then
P1_ERROR<55:52>, CMD, will contain the PCI Command of the transaction that caused the error.
P1_ERROR<47:18>, ADDR, will contain address bits <31:2> of the starting PCI Address of the transaction that caused the error.
P1_ERROR<17:16> will be 00b if not a DAC operation; 01b if via DAC SG to Window 3; and 1xb via monster window.
|
| Recovery: | There is no recovery for this defective PCI master transaction. |
| Faulting FRU: | Option |
| 202h - System detected PCI Invalid Scatter/Gather Page Table Entry Error (SGTE) |
| Indicator: | DIR0<62> = 1 and P0_ERROR<4> = 1 and P0_ERROR<51> = 0 from PCHIP0 or
DIR0<61> = 1 and P1_ERROR<4> = 1and P1_ERROR<51> = 0 from PCHIP1 |
| Description: | A PCI invalid scatter/gather page table entry error has been detected by a target PChip 0 or 1. This is processed through the 660-error handler. |
| Analysis: |
If PChip 0 error
P0_ERROR<55:52>, CMD, will contain the PCI Command of the transaction that caused the error.
P0_ERROR<47:18>, ADDR, will contain address bits <31:2> of the starting PCI Address of the transaction that caused the error.
P0_ERROR<17:16> will be 00b if not a DAC operation; 01b if via DAC SG to Window 3; and 1xb via monster window.
If PChip 1 error then
P1_ERROR<55:52>, CMD, will contain the PCI Command of the transaction that caused the error.
P1_ERROR<47:18>, ADDR, will contain address bits <31:2> of the starting PCI Address of the transaction that caused the error.
P1_ERROR<17:16> will be 00b if not a DAC operation; 01b if via DAC SG to Window 3; and 1xb via monster window.
|
| Recovery: | There is no recovery for this defective PCI master transaction. |
| Faulting FRU: | Option |
| 202h - System detected PCI Address/Command Parity Error (APE) |
| Indicator: | DIR0<62> = 1 and P0_ERROR<5> = 1 and P0_ERROR<51> = 0 from PCHIP0 or
DIR0<61> = 1 and P1_ERROR<5> = 1and P1_ERROR<51> = 0 from PCHIP1 |
| Description: | A target PChip 0 or 1 detected a PCI address/command cycle parity error. This is processed through the 660-error handler. |
| Analysis: |
If PChip 0 error
P0_ERROR<55:52>, CMD, will contain the PCI Command of the transaction that caused the error.
P0_ERROR<47:18>, ADDR, will contain address bits <31:2> of the starting PCI Address of the transaction that caused the error.
P0_ERROR<17:16> will be 00b if not a DAC operation; 01b if via DAC SG to Window 3; and 1xb via monster window.
If PChip 1 error then
P1_ERROR<55:52>, CMD, will contain the PCI Command of the transaction that caused the error.
P1_ERROR<47:18>, ADDR, will contain address bits <31:2> of the starting PCI Address of the transaction that caused the error.
P1_ERROR<17:16> will be 00b if not a DAC operation; 01b if via DAC SG to Window 3; and 1xb via monster window.
|
| Recovery: | There is no recovery for this defective PCI master transaction. |
| Faulting FRU: | Option |
| 202h - System detected PCI Target Abort Error (TA) |
| Indicator: | DIR0<62> = 1 and P0_ERROR<6> = 1 and P0_ERROR<51> = 0 from PCHIP0 or
DIR0<61> = 1 and P1_ERROR<6> = 1and P1_ERROR<51> = 0 from PCHIP1 |
| Description: | PChip 0 or 1 detected a PCI target abort when acting as a master. This is processed through the 660-error handler. |
| Analysis: |
If PChip 0 error
P0_ERROR<55:52>, CMD, will contain the PCI Command of the transaction that caused the error.
P0_ERROR<47:18>, ADDR, will contain address bits <31:2> of the starting PCI Address of the transaction that caused the error.
P0_ERROR<17:16> will be 00b if not a DAC operation; 01b if via DAC SG to Window 3; and 1xb via monster window.
If PChip 1 error then
P1_ERROR<55:52>, CMD, will contain the PCI Command of the transaction that caused the error.
P1_ERROR<47:18>, ADDR, will contain address bits <31:2> of the starting PCI Address of the transaction that caused the error.
P1_ERROR<17:16> will be 00b if not a DAC operation; 01b if via DAC SG to Window 3; and 1xb via monster window. |
| Recovery: | There is no recovery for this defective PCI target transaction. |
| Faulting FRU: | Option |
| 202h - System detected PCI Bus Read Data Parity Error -(RDPE) |
| Indicator: | DIR0<62> = 1 and P0_ERROR<7> = 1 and P0_ERROR<51> = 0 from PCHIP0 or
DIR0<61> = 1 and P1_ERROR<7> = 1and P1_ERROR<51> = 0 from PCHIP1 |
| Description: | PChip 0 or 1 detected a PCI read data parity error when acting as a master. This is processed through the 660-error handler. |
| Analysis: |
If PChip 0 error
P0_ERROR<55:52>, CMD, will contain the PCI Command of the transaction that caused the error.
P0_ERROR<47:18>, ADDR, will contain address bits <31:2> of the starting PCI Address of the transaction that caused the error.
P0_ERROR<17:16> will be 00b if not a DAC operation; 01b if via DAC SG to Window 3; and 1xb via monster window.
If PChip 1 error then
P1_ERROR<55:52>, CMD, will contain the PCI Command of the transaction that caused the error.
P1_ERROR<47:18>, ADDR, will contain address bits <31:2> of the starting PCI Address of the transaction that caused the error.
P1_ERROR<17:16> will be 00b if not a DAC operation; 01b if via DAC SG to Window 3; and 1xb via monster window.
|
| Recovery: | There is no recovery for this defective PCI target transaction. |
| Faulting FRU: | Option |
| 202h - System detected PCI No Device Select Error (NDS) |
| Indicator: | DIR0<62> = 1 and P0_ERROR<8> = 1 and P0_ERROR<51> = 0 from PCHIP0 or
DIR0<61> = 1 and P1_ERROR<8> = 1and P1_ERROR<51> = 0 from PCHIP1 |
| Description: | A PCI no device select error has been detected by a master PChip 0 or 1 and the transaction has been terminated by PChip master abort. This is processed through the 660-error handler. |
| Analysis: |
If PChip 0 error
P0_ERROR<55:52>, CMD, will contain the PCI Command of the transaction that caused the error.
P0_ERROR<47:18>, ADDR, will contain address bits <31:2> of the starting PCI Address of the transaction that caused the error.
P0_ERROR<17:16> will be 00b if not a DAC operation; 01b if via DAC SG to Window 3; and 1xb via monster window.
If PChip 1 error then
P1_ERROR<55:52>, CMD, will contain the PCI Command of the transaction that caused the error.
P1_ERROR<47:18>, ADDR, will contain address bits <31:2> of the starting PCI Address of the transaction that caused the error.
P1_ERROR<17:16> will be 00b if not a DAC operation; 01b if via DAC SG to Window 3; and 1xb via monster window.
|
| Recovery: | There is no recovery for this defective PCI target transaction. |
| Faulting FRU: | Option |
| 202h - System detected PCI Retry Time Out Error (RTO) |
| Indicator: | DIR0<62> = 1 and P0_ERROR<9> = 1 and P0_ERROR<51> = 0 from PCHIP0 or
DIR0<61> = 1 and P1_ERROR<9> = 1and P1_ERROR<51> = 0 from PCHIP1 |
| Description: | A PCI retry time out error has been detected by a master PChip 0 or 1 after 2**24 retry responses. This is processed through the 660-error handler. |
| Analysis: |
If PChip 0 error
P0_ERROR<55:52>, CMD, will contain the PCI Command of the transaction that caused the error.
P0_ERROR<47:18>, ADDR, will contain address bits <31:2> of the starting PCI Address of the transaction that caused the error.
P0_ERROR<17:16> will be 00b if not a DAC operation; 01b if via DAC SG to Window 3; and 1xb via monster window.
If PChip 1 error then
P1_ERROR<55:52>, CMD, will contain the PCI Command of the transaction that caused the error.
P1_ERROR<47:18>, ADDR, will contain address bits <31:2> of the starting PCI Address of the transaction that caused the error.
P1_ERROR<17:16> will be 00b if not a DAC operation; 01b if via DAC SG to Window 3; and 1xb via monster window.
|
| Recovery: | There is no recovery for this defective PCI target transaction. |
| Faulting FRU: | Option |
| 202h - System detected Uncorrectable ECC Error (UECC) |
| Indicator: | P0_CTL<18>= 1 and DIR0<62> = 1 and P0_ERROR<10> = 1 and P0_ERROR<51> = 0 from PCHIP0 or
P1_CTL<18>= 1 and DIR0<61> = 1and P1_ERROR<10> = 1 and P1_ERROR<51> = 0 from PCHIP1 |
| Description: | An uncorrectable system ECC error has been detected by PChip 0 and/or 1. This is processed through the 660-error handler. |
| Analysis: |
If PChip 0 error
P0_ERROR<63:56>, SYN, will contain the ECC Syndrome of the error
P0_ERROR<55:52>, CMD, will contain the type of DMA operation. Refer to Table 5-27 for the definitions
P0_ERROR<50:16>, ADDR, will contain the system address bits <34:3> of the erroneous quadword.
If PChip 1 error then
P1_ERROR<63:56>, SYN, will contain the ECC Syndrome of the error
P1_ERROR<55:52>, CMD, will contain the type of DMA operation. Refer to Table 5-28 for the definitions
P1_ERROR<50:16>, ADDR, will contain the system address bits <34:3> of the erroneous quadword.
|
| Recovery: | Typically there is no recovery for this defect within the PCI memory space unless the operating system is capable of swapping out the erred memory map page(s) and still able to process PCI transactions properly. |
| Faulting FRU: | Option |